Boundary scan path method and system with functional and non-functional scan cell memories

ABSTRACT

This patent describes a boundary scan system where memories, i.e. flip flops or latches, used in data scan cells are also used functionally, but memories used in control scan cells are dedicated for test and not used functionally. The control scan cells can be scanned while the circuit is in functional mode, since their memories are dedicated. However, the data scan cells can only be scanned after the circuit transitions into test mode, since their memories are shared. This boundary scan system advantageously provides; (1) lower test circuitry overhead since the data scan cells use shared memories, (2) safe entry into test mode since the control scan cells can be scanned during functional mode to pre-load safe control conditions, and (3) avoidance of floating (i.e. 3-state) busses that can cause high current situations.

BACKGROUND OF THE INVENTION

[0001] In FIG. 1, a prior art example of a dedicated boundary scan pathor register exists around a master circuit 102, a slave 1 circuit 104,and a slave 2 circuit 106. The master circuit, such as a DSP, CPU, ormicro-controller, is a circuit that controls the slaves. The slavecircuits are circuits being controlled by the master, such as RAM, ROM,cache, A/D, D/A, serial communication circuits, or I/O circuits. Themaster and slave circuits could exist as individual intellectualproperty core sub-circuits inside an integrated circuit or IC, or asindividual ICs assembled on a printed circuit board or multi-chip module(MCM). The scan paths 108-112 around each circuit are connected togetherserially and to a test data input (TDI) 114, which supplies test data tothe scan paths, and a test data output (TDO) 116, which retrieves datafrom the scan paths.

[0002] For simplification, only a portion of the scan paths 108-112 ofeach circuit is shown. The scan paths of FIG. 1 are designed usingdedicated scan cells, indicated by capital letters (C) and (D) incircles. The word dedicated means that the cell's circuitry is used fortesting purposes and is not shared for functional purposes. The scancells are located between the internal circuitry and the input buffers128 and output buffers 130 of the slaves and master circuit.

[0003] In FIG. 2, an example of a dedicated scan cell consists ofmultiplexer 1 (MX1) 202, memory 1 (M1) 204, memory 2 (M2) 206, andmultiplexer 1 (MX2) 208. This scan cell is similar to scan cellsdescribed in IEEE standard 1149.1, so only a brief description will beprovided. During operation in a functional mode, functional data passesfrom the functional data input (FDI) 212 to the functional data output(FDO) 214. In a functional mode, control inputs 210 to the scan cellcan: (1) cause FDI data to be loaded into M1 via MX1 during a captureoperation; (2) scan data from TDI 216 through MX1 and M1 to TDO 218during a shift operation; and (3) cause data in M1 to be loaded into M2during an update operation. Neither the capture, shift, nor updateoperation disturbs the functional data passing between FDI and FDO. Thusthe scan cell of FIG. 2 can be accessed and pre-loaded with test datawhile the cell is in functional mode. The data scan cell (D) associatedwith the D31 output of slave 1 104 has connections corresponding to theFDI 212, TDI 216, FDO 214, and TDO 218 signal connections of the FIG. 2scan cell.

[0004] During a functional mode of operation of the circuit in FIG. 1,data is transferred from one of the slaves to the master via a 32-bitdata bus (D0-31), indicated by the wired bus connections 126. In afunctional mode the scan cells are transparent, allowing functionalcontrol and data signals to pass freely through the cells. In thisexample, the master enables slave 1 to transfer data by the ENA1 controlsignal, which is output from the master to slave 1. Likewise the masterenables slave 2 to transfer data by the ENA2 control signal, which isoutput from the master to slave 2. While only two slave circuits areshown, any number could be similarly connected to and operated by themaster. Since all the scan cells of the scan paths 108-112 are dedicatedfor test, they can be scanned from TDI to TDO without disturbing thefunctional mode of the FIG. 1 circuit.

[0005] As mentioned, being able to scan data into the scan paths duringfunctional mode allows pre-loading an initial test pattern into the scanpaths. The initial test pattern establishes both a data test pattern inthe data scan cells (D) and a control test pattern in the control scancells (C). By pre-loading an initial test pattern into the scan paths,the circuits can safely transition from a functioning mode to a testmode without concern over bus contention between the slave circuit'sdata busses. For example, the ENA1 122 and ENA2 124 control scan cells(C) can be pre-loaded with control data to insure that only one of theslave's D0-31 data busses is enabled to drive the wired bus connection126. Maintaining output drive on one of the slave data busses upon entryinto test mode prevents the wired data bus 126 from entering into afloating (i.e. 3-state) condition. Preventing bus 126 from floating isdesirable since a floating input to input buffers 128 of master 102could cause a high current condition.

[0006] When test mode is entered, functional operation of the master andslave circuits stop and the scan cells in the scan paths take control ofthe master and slave circuit's data and control signal paths. A datascan cell (D) exists on each of the 32-bit data signal paths of eachcircuit 102-106, and a control scan cell (C) exists on each of the ENA1and ENA2 control paths of each circuit 102-106.

[0007] Having dedicated data and control scan cells located as shown inFIG. 1, enables safe test entry and easy interconnect testing of thewiring between the master and slave circuits when the scan paths areplaced in test mode. During interconnect test mode, a capture, shift,and update control sequence, such as that defined in IEEE standard1149.1, can be used to control the scan paths.

[0008] To prevent contention between slave 1 and slave 2 data outputs126 during the capture, shift, and update control sequence, the 3-statecontrol outputs 118-120 of the ENA1 and ENA2 control scan cells 122-124do not ripple during the capture and shift part of the control inputsequence. This is accomplished by having the data in M2 of FIG. 2 beoutput, via MX2, during the capture and shift operation. Only during theupdate part of the control input sequence are the outputs 118-120 of thecontrol scan cells 122-124 allowed to change state by new data beingloaded into M2. Similarly, the outputs from the data scan cells (D) donot ripple during capture and shift operations, but rather change stateonly during the update part of the control input sequence.

[0009] In FIG. 3, a prior art example of a shared boundary scan pathexists around a master 302 and slave circuits 304-306. As in FIG. 1, thescan paths 308-312 around each circuit are connected together seriallyand to a test data input (TDI), which supplies test data to the scanpaths, and a test data output (TDO), which retrieves data from the scanpaths. The scan paths of FIG. 3 are designed using shared scan cells (C)and (D), i.e. the scan cell memory is shared for both test andfunctional purposes. As an aid to indicate use of shared scan cells asopposed to dedicated scan cells, the shared scan cells of FIG. 3 andsubsequent figures are shown positioned outside the boundary scan paths308-312 and in the functional circuits. The dedicated scan cells of FIG.1 were shown positioned inside the boundary scan paths 108-112. Again,for simplification, only a portion of each circuit's boundary scan pathis shown.

[0010] In FIG. 4, an example of a conventional shared scan cell consistsof a multiplexer (MX) 402 and a memory (M) 404. During a functional modeof operation, control inputs 406 form a path between FDI 408 and thedata input of M 404 via MX 402, to allow functional data to be clockedfrom FDI to FDO 410. During a test mode, the control inputs 406 causeFDI data to be clocked into M via MX during a capture operation, andcause test data to be clocked from TDI 412 to TDO 414 during a shiftoperation. Since M 404 is used functionally, it cannot be accessed andpre-loaded with test data as can the scan cell of FIG. 2. Thus theability to access and pre-load test data while the master and slavecircuits of FIG. 3 operate functionally is one of the key distinctionsbetween dedicated (FIG. 2) and shared (FIG. 4) scan cells.

[0011] In FIG. 3, the data scan cell associated with the D31 output ofslave 1 304 is labeled to indicate the FDI 408, TDI 412, FDO 410, andTDO 414 signal connections of the FIG. 4 scan cell.

[0012] During the functional mode of the circuit in FIG. 3, as in FIG.1, data is transferred from one of the slaves to the master via the32-bit data bus (D0-31) through shared connections 326. The masterenables data transfer from slave 1 or slave 2 via the ENA1 and ENA2control signals, respectively. Since the scan cells of the scan pathsare shared and used functionally, they cannot be scanned from TDI to TDOwithout disturbing the functional mode of the circuits. Not being ableto scan data into the scan paths during functional mode preventspre-loading an initial test pattern into the scan paths.

[0013] By not being able to pre-load an initial test pattern into thescan paths, the slave circuits are put at risk of not safelytransitioning into the test mode from the functional mode. Thissituation occurs due to the timing domains of the functional and testmodes not being synchronous to one another, which results inasynchronous functional to test mode switching.

[0014] For example, if the circuits of FIG. 3 switched from thefunctional mode timing domain to a test mode timing domain, apossibility exists that the D0-31 output buffers of slave 1 and 2 couldboth be enabled as a result of an asynchronous mode switch that causedscan cell ENA1 322 and scan cell ENA2 324 to both output enableconditions on wires 318 and 320. This would force a voltage contentionsituation between slave 1 and 2, resulting in the output buffers beingdamaged or destroyed. This voltage contention situation does not occurin the boundary scan path of FIG. 1 since an initial safe test patternis preloaded into the scan cells prior to the functional to test modeswitching step.

[0015] Once in a test mode, the scan path of FIG. 3 can be accessed toshift in test data. During shift operations the outputs 318-320 of thecontrol scan cells 322-324 ripple as data shifts through the cells. Thisoutput ripple from the control scan cells can cause the D0-31 outputbuffers of the slaves to be enabled and disabled during the shiftoperation. This control output ripple causes the output buffers ofslaves 1 and 2 to be simultaneously enabled, again creating buscontention between the slaves. This voltage contention situation doesnot occur in the boundary scan path of FIG. 1 since M 206 maintains asafe control output, via MX 208, during shift operations.

[0016] In FIG. 5, one prior art technique prevents the above-mentionedtwo voltage contention situations. The technique is based on providingadditional circuitry and control inputs to enable or disable the slave'soutput buffers during test mode entry and again during each test modeshift operation. A signal gating circuit 528 is inserted into signalpath 518 of slave 504 and a signal gating circuit 530 is inserted intosignal path 520 of slave 506. A control signal C1 532 is added as aninput to circuits 528 and 530. When C1 is in a first state, the ENA1 andENA2 outputs from scan cells 522 and 524 are allowed to pass throughcircuits 528 and 530 to enable or disable the output buffers of slaves504 and 506. However, when C1 is in a second state, the outputs ofcircuits 528 and 530 are forced, independent of ENA1 and ENA2, todisable the output buffers of slaves 504 and 506. By controlling C1 tothe second state during the transition from functional mode to testmode, the first above mentioned voltage contention situation can beavoided. By again controlling C1 to the second state during each shiftoperation that occurs during test mode, the second above mentionedvoltage contention situation can be avoided.

[0017] While the technique described above solves the voltage contentionsituations, it does so by introducing a floating (i.e. 3-state)condition on data bus 526. As described above, the output buffers ofslaves 504 and 506 are disabled during test mode entry and during eachshift operation. With the output buffers disabled, data bus 526 is notdriven and may float to a voltage level that could turn on both inputtransistors of the input buffers of master 502. This could result in alow impedance path between the master's supply and ground voltages,potentially damaging or destroying the input buffers of master 502.

BRIEF SUMMARY OF THE INVENTION

[0018] This invention provides a boundary scan system where memories,i.e. flip flops or latches, used in data scan cells are also usedfunctionally, but memories used in control scan cells are dedicated fortest and not used functionally. The control scan cells can be scannedwhile the circuit is in functional mode, since their memories arededicated. However, the data scan cells can only be scanned after thecircuit transitions into test mode, since their memories are shared.This boundary scan system advantageously provides: (1) lower testcircuitry overhead since the data scan cells use shared memories; (2)safe entry into test mode since the control scan cells can be scannedduring functional mode to pre-load safe control conditions; and (3)avoidance of floating (i.e. 3-state) busses that can cause high currentsituations.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0019]FIG. 1 is a simplified block diagram of a known boundary scan patharound a master IC/core and two slave IC/cores;

[0020]FIG. 2 is a schematic diagram of a known dedicated scan cell;

[0021]FIG. 3 is a simplified block diagram of a known shared boundaryscan path around a master IC/core and two slave IC/cores;

[0022]FIG. 4 is a schematic diagram of a known shared scan cell;

[0023]FIG. 5 is a simplified block diagram of a known boundary scan patharound a master IC/core and two slave IC/cores with additional circuitsto avoid voltage contention situations;

[0024]FIG. 6 is a simplified block diagram of a boundary scan patharound a master IC/core and two slave IC/cores according to theinvention;

[0025]FIG. 7 illustrates the boundary scan system of FIG. 6 modified toinclude additional memories in the scan path;

[0026]FIG. 8 is a schematic diagram of re-synchronization memories; and

[0027]FIG. 9 is a simplified block diagram of a modified boundary scanpath.

DETAILED DESCRIPTION OF THE INVENTION

[0028] In FIG. 6, a boundary scan system according to the presentinvention comprises a master circuit 602 operable to receive datatransmitted from two slave circuits 604-606. The circuits 602-606 eachhave a boundary scan path 608-612, a portion of which is shown. The scanpaths around each circuit are connected together serially and to TDI,which supplies test data to the scan paths, and TDO, which retrievesdata from the scan paths. A first difference between the known scanpaths and the scan path of FIG. 6 is that the control scan cells (C) ofthe scan paths in FIG. 6 are designed as dedicated scan cells, and thedata scan cells (D) are designed as shared cells. A second difference isthat the scan path has two configurations. In one configuration, thecontrol cells reside on a serial path (path1) separate from the serialpath (path2) on which the data scan cells reside. In another scanconfiguration, the control scan cells reside on the same serial path(path2) on which the data scan cells reside.

[0029] Multiplexers 636-640 are provided for selecting the serial paths(path1) to be connected serially together between TDI and TDO, or forselecting the serial paths (path2) to be connected serially togetherbetween TDI and TDO. Control for the multiplexers to select aconfiguration of either path1 or path 2 between TDI and TDO comes from aSEL signal, which is connected to the select input of each multiplexer636-640.

[0030] If the master and slave circuits and their associated boundaryscan paths are realized as embedded cores within an IC, the SEL signal634 may come from an IEEE 1149.1 instruction register on the IC, anotherregister or circuit on the IC, or from an input pin on the IC. However,if the master and slave circuits and their associated boundary scanpaths are realized as separate ICs on a board or MCM, the SEL signal maycome from an IEEE 1149.1 instruction register on each of the ICs,another register or circuit on each of the ICs, or from an input pin oneach of the ICs. In the case, where the master and slaves are separateICs and where the SEL signal comes from an IEEE 1149.1 instructionregister, or another register or circuit, on each IC, the SEL signalwill not be bussed to the same wire 634 as shown in FIG. 6, but ratherindividual SEL signal wires will exist between the IEEE 1149.1instruction register, or another register or circuit, and multiplexers636-64 on each of the individual ICs.

[0031] During a functional mode of operation of the circuit in FIG. 6data is transferred from one of the slaves to the master via the 32-bitdata bus (D0-31) on connections 626. The master enables data transferfrom slave 1 or slave 2 via the ENA1 and ENA2 control signals,respectively. Since the data scan cells of the scan paths are shared andused functionally, they cannot be scanned from TDI to TDO withoutdisturbing the functional mode of the circuits. However, since thecontrol scan cells of the scan paths are not shared, they can be scannedfrom TDI to TDO without disturbing the functional mode of the circuit.

[0032] By scanning the control scan cells by themselves, via path 1, itis possible to pre-load, while the master and slave circuits arefunctioning, a control test pattern into the control scan cells. Thiscontrol test pattern can be advantageously used to establish the testmode state of the slave data busses to insure that no contention betweenthe data busses occurs upon switching from functional mode to test mode.For example, a control test pattern may be scanned into the control scancells via path 1 to, upon entry into test mode, enable slave 1's databus and disable slave 2's data bus or to disable slave 1's data bus andenable slave 2's data bus. By designing the control scan cells asdedicated scan cells, and by selectively grouping only the control scancells onto path1 between TDI and TDO, it is possible to pre-load acontrol test pattern to safely transition into test mode without slavebus contention and without disabling both slave buses.

[0033] When a test mode is entered, functional operation of the circuitsstop and the scan cells take control of the master and slave circuit'sdata and control signal paths. The state of the data scan cells will beunknown at the beginning of the test since they could not be scannedduring functional mode. That is not a problem however since the knownvalues scanned into the control scan cells prevent any contention on thedata busses. After the test mode is entered, the multiplexers 636-640are controlled to group both the control and data scan cells onto path2. A first combined data and control scan cell test pattern is thenshifted into the scan path via path2 and updated to start the test. Theoutputs of the control scan cells of FIG. 6 do not ripple during shiftoperations since they use the scan cell design of FIG. 2, thus buscontention between slaves is prevented during shift operations.

[0034] The outputs of the data scan cells do ripple during shiftoperation since they use the scan cell design of FIG. 4. However, thisdata ripple does not harm the circuit or cause bus contention since onlyone slave is enabled at a time to output data onto bus 626. While onlytwo slave circuits 604 and 606, each with an associated boundary scanportions 608 and 612, were shown in FIG. 6, any number of slave circuitsand associated boundary scan portions could be similarly connected tothe master circuit 602 and associated boundary scan portion 610.

[0035] In FIG. 7, the boundary scan system of FIG. 6 includes additionalmemories 702-712 in the serial paths path1. Depending upon the layout ofthe IC or core master and slave circuits, the wire running between thescan inputs and outputs of the control scan cells in path 1 may becomelong when bypassing a large number of shared data scan cells. If thewiring becomes to long the setup and hold times of the control scancells may be violated, resulting in shift operation failures throughpath 1.

[0036] To prevent shift operation failures, one or moreresynchronization memories 702-712 may be located in path1 between thescan outputs and scan inputs of the control scan cells. Theresynchronization memories, typically D flip flops as shown in FIG. 8,would be located in scan path1 such that the control data shiftedthrough path1 passes through a shorter length of wiring between thecontrol scan cells and resynchronization memories, thus managing thesetup and hold timing for reliably shifting data through path 1.

[0037] If resynchronization memories are used, the bit length of path 1will grow by the number of resynchronization memories. To compensate forthis bit length growth, each test pattern shifted into path1 will needto be augmented to include appropriately positioned resynchronizationdata bits during shift operations. In FIG. 7, the resynchronizationmemories 702-712 are not necessary when shift operations occur throughpath2, since the shared data scan cells are not being bypassed. Thusscan path2 does not include the resynchronization memories, and the testpatterns shifted into scan path2 advantageously do not need to beaugmented to include the aforementioned resynchronization data bits.

[0038] In FIG. 9, a boundary scan system consists of master circuit 902and slave circuits 904 and 906. Boundary scan portion 908 of slave 904is similar to boundary scan portion 608 of FIG. 6 with the exceptionthat it includes an additional input (IN) to slave circuit 904 and anassociated dedicated data scan cell 922. Also, boundary scan portion 912of slave 906 is similar to boundary scan portion 612 of FIG. 6 with theexception that it includes an additional output (OUT) from slave circuit906 and an associated dedicated data scan cell 924.

[0039] The arrangement of FIG. 9 indicates that dedicated data scancells 922 and 924 (i.e. a scan cell similar to that of FIG. 2) can beincluded in both path1 and path2 shift operations. When the path1 serialpaths are selected between TDI and TDO, data can be shifted through thecontrol scan cells (C) and the 922 and 924 data scan cells (D) of FIG. 9during functional mode. When the path2 serial paths are selected betweenTDI and TDO, data can be shifted through all the scan cells of FIG. 9,both shared and dedicated, during test mode.

[0040] While specific signal types, i.e. data and control, have beenassociated with shared and dedicated scan cells in FIGS. 6 and 9, itshould be understood that in general shared and dedicated scan cells areindependent of signal types. What is important is to associate dedicatedscan cells with signal types that need to be preconditioned with dataprior to entry into test mode. Shared scan cells, on the other hand, canbe associated with signal types that do not need to be preconditionedwith data prior to test mode entry.

[0041] The arrangements of FIGS. 6 and 9 and their accompanyingdescriptions have described a boundary scan path system consisting ofgroups of dedicated scan cells and groups of shared scan cells.Multiplexers within the boundary scan path system allow partitioning theboundary scan path to allow serial access to occur either to only thededicated scan cell groups or to both the dedicated and shared scancells groups. The ability to serially access dedicated scan cells withina boundary scan system independent of the shared scan cells, and whilethe functional circuits operate, advantageously allows loading certainkey data signals which facilitate safe entry into test mode from thefunctional mode.

[0042] The arrangements of FIGS. 6 and 9 and their accompanyingdescriptions have also described a process for safely transitioningcircuits and their associated boundary scans paths from their functionalmode to test mode. The process can be summarized as: (1) configuring theboundary scan path system to contain only dedicated scan cells betweenTDI and TDO, (2) performing a shift operation to load data into thededicated scan cells, (3) entering the boundary scan test mode, (4)configuring the boundary scan path system to contain all scan cells,both shared and dedicated, between TDI and TDO, and (5) performing ashift operation to load data into all the scan cells.

[0043] The arrangement of FIG. 7 and its accompanying description hasdescribed why resynchronization memories may be needed and how they maybe used to register data transfers across bypassed sections of sharedscan cells to resolve setup and hold timing problems that might existbetween a sending and receiving dedicated scan cell.

[0044] Although the present invention has been described in accordanceto the embodiments shown in the figures, one of ordinary skill in theart will recognize there could be variations to these embodiments andthose variations should be within the spirit and scope of the presentinvention. Accordingly, modifications may be made by one ordinarilyskilled in the art without departing from the spirit and scope of theappended claims.

I claim:
 1. An integrated circuit comprising; a test data input terminaland a test data output terminal; a boundary scan path including amixture of serially connected dedicated and shared boundary scan cells,said boundary scan path having an input and an output; a firstconnection formed between said test data input terminal and saidboundary scan path input, and; a second connection formed between saidtest data output terminal and said boundary scan path output.
 2. Anintegrated circuit comprising; a boundary scan path including one ormore groups of serially connected dedicated boundary scan cells and oneor more groups of serially connected shared boundary scan cells, saidboundary scan path having an input and an output; and multiplexercircuitry associated with said boundary scan path for selectivelybypassing said one or more shared boundary scan cell groups such thatonly the one or more dedicated boundary scan cell groups exist betweensaid input and output.
 3. The integrated circuit of claim 2 furthercomprising; a test data input terminal and a test data output terminal;a first connection formed between said test data input terminal and saidboundary scan path input, and; a second connection formed between saidtest data output terminal and said boundary scan path output.
 4. Theintegrated circuit of claim 2 further comprising; at least oneresynchronization memory located in the serial path between at least twoof said dedicated boundary scan cell groups.
 5. An integrated circuitcomprising; a first boundary scan path portion having an input and anoutput and one or more dedicated scan cells coupled therebetween; asecond boundary scan path portion having an input and an output and oneor more shared scan cells coupled therebetween; a multiplexer havingfirst and second inputs; a first connection formed between the output ofsaid first boundary scan path portion and said first multiplexer input;a second connection formed between the output of said second boundaryscan path portion and said second multiplexer input; and, a thirdconnection formed between the output of said first boundary scan pathportion and said input to said second boundary scan path portion.
 6. Theintegrated circuit of claim 5 further comprising; a least oneresynchronization memory located in the first connection formed betweenthe output of said first boundary scan path portion and said firstmultiplexer input.
 7. An integrated circuit comprising; a boundary scanpath having at least one resynchronization memory located in the serialpath between two boundary scan cells.
 8. A process of entering into aboundary scan test mode comprising the steps of; performing a firstserial communication to load data into only a subset of the scan cellswithin the boundary scan path, entering the boundary scan test mode,and; performing a second serial communication to load data into all thescan cells within the boundary scan path.
 9. An intellectual propertycore circuit within an integrated circuit, said intellectual propertycore circuit comprising; a boundary scan path having an input and anoutput, said boundary scan path containing a mixture of seriallyconnected shared and dedicated scan cells; and multiplexer circuitry forselectively partitioning the boundary scan path to include only thededicated scan cells between said input and output.
 10. An integratedcircuit comprising a test data input terminal and a test data outputterminal; a plurality of intellectual property core circuits eachincluding a boundary scan path containing and input lead and an outputlead and a mixture of dedicated and shared scan cells located seriallybetween said input and output leads; connections formed between theinput and output leads of the boundary scan paths such that the outputof a leading boundary scan path connects to an input of a trailingboundary scan path to form a serial arrangement of boundary scan paths;an input connection formed between the test data input terminal and theinput lead of the first boundary scan path of said serial arrangement ofboundary scan paths; and an output connection formed between the testdata output terminal and the output lead of the last boundary scan pathof said serial arrangement of boundary scan paths.
 11. A boundary scansystem comprising: A. a test data input; B. a test data output; C. atleast one control scan cell having a memory capable of scanning a testsignal while carrying a functional signal; D. at least one data scancell having a memory that is used for both test and functional signals;E. a boundary scan path between the test data input and the test dataoutput, the path having two configurations, the first configurationincluding the at least one control scan cell and excluding the at leastone data scan cell, and the second configuration including both the atleast one control scan cell and the at least one data scan cell; and F.a multiplexer in the path selecting between the first and secondconfigurations.